ACE16k: A programmable focal plane vision processor with 128 x 128 resolution

Comunicación presentada al "ECCTD’01" celebrada del 28 al 31 de Agosto del 2001 en Finlandia.This paper presents a new generation 128x128 Focal Plane Analog Programmable Array Processor (FPAPAP), from a system level perspective. The design has recently sent to fabrication in a 0.35μm standard digital 1P-5M CMOS Technology. The chip has been designed to achieve the high-speed and moderate-accuracy constraints of most real time image processing applications. It has been designed to be easily embedded in conventional digital hosting systems: external data interchange and control are completely digital. The chip contains close to four millions transistors, 80% of them working in analog mode, and exhibits a relatively low power consumption (<4W, i.e. less than 1mW per transistor). Experimental results are expected for the date of paper presentation.This work has been partially funded by ONR-NICOP N68171-98-C-9004 and DICTAM IST-1999-19007.Peer reviewe

Residual oxides detection and measurement in stainless steel production lines

In this paper, we present a system to detect and measure the amount of residual oxide stains remaining in the surface of stainless steel coils after the pickling process in a production line. The system is able to acquire clear images of the stainless steel surface with the appropriate illumination and magnification, while it is being produced. These images are processed and analyzed in real time in order to detect and measure the oxide stains which typically are between 50 and 200 microns in size. We present here an outline of the acquisition system and the image processing algorithm which has been designed to detect this sort of defect.Peer Reviewe

Ultra-high frame rate focal plane image sensor and processor

Application examples of a fully-programmable analogic focal plane array processor are introduced. One mixed-signal sensory/processing chip is presented, which is capable to capture, process, and evaluate over 10,000 images in a second. Morphological analysis of silhouettes and sparks were done and real-time decision making was performed running on this extraordinary high frame-rate. © 2002 IEEE.Peer Reviewe

A 1000 FPS at 128×128 vision processor with 8-bit digitized I/O

This paper presents a mixed-signal programmable chip for high-speed vision applications. It consists of an array of processing elements, arranged to operate in accordance with the principles of single instruction multiple data (SIMD) computing architectures. This chip, implemented in a 0.35-μm fully digital CMOS technology, contains ∼ 3.75 M transistors and exhibits peak performance figures of 330 GOPS (8-bit equivalent giga-operations per second), 3.6 GOPS/mm2 and 82.5 GOPS/W. It includes structures for image acquisition and for image processing, meaning that it does not require a separate imager for operation. At the sensory side, integration and log-compression sensing circuits are embedded, thus allowing the chip to handle a large variety of illumination conditions. At the processing plane, analog and digital circuits are employed whose parameters can be programmed and their architecture reconfigured for the realization of software-coded processing algorithms. The chip provides, and accepts, 8-bit digitized data through a 32-bit bidirectional data bus which operates at 120 MB/s. Experimental results show that frame rates of 1000 frames per second (FPS) can be achieved under room illumination conditions; applications using exposures of about 50 μs have been recently reached by using special illumination setups. The chip can capture an image, run approximately 150 two-dimensional linear convolutions, and download the result in 8-bit digital format, in less than 1 ms. This feature, together with the possibility of executing sequences of user-definable instructions (stored on a full-custom 32-kb on-chip memory), and storing intermediate results (up to 8 grayscale images) makes the chip a true general-purpose sensory/processing device.This work was supported in part by Research Project LOCUST IST-2001-38097, and by the Office of Naval Research under Project N000140210884.Peer Reviewe

ACE4k: An analog I/O 64×64 visual microprocessor chip with 7-bit analog accuracy

This paper describes a full-custom mixed-signal chip which embeds distributed optical signal acquisition, digitally-programmable analog parallel processing, and distributed image memory cache on a common silicon substrate. This chip, designed in a 0.5 μm standard CMOS technology contains around 1.000.000 transistors, of which operate in analog mode; it is hence one the most complex mixed-signal chip reported to now. Chip functional features are: local interactions, spatial-invariant array architecture; programmable local interactions among cells; randomly-selectable memory of instructions (elementary instructions are defined by specific values of the cell local interactions); random storage/retrieval of intermediate images; capability to complete algorithmic image processing tasks controlled by the user-selected stored instructions and interacting with the cache memory, etc. Thus, as illustrated in this paper, the chip is capable to complete complex spatio-temporal image processing tasks within short computation time ( 7-bits equivalent accuracy in the internal analog operations, which has been confirmed by experimental measurements. Such 7-bits accuracy is enough for most image processing applications. ACE4k has been demonstrated capable to implement up to 30 templateσ-either directly or through template decomposition. This means the 100% of the 3 × 3 linear templates reported in Roska et al. 1998, [1]. Copyright © 2002 John Wiley & Sons, Ltd.Funded by: ONR-NICOP. Grant Number: N68171-98-C-9004; DICTAM. Grant Number: IST-1999-19007 and CICYT TIC. Grant Number: 1999 0826.Peer Reviewe

ACE16k: a 128x128 focal plane analog processor with digital I/O

This paper presents a new generation 128x128 Focal-Plane Analog Programmable Array Processor -FPAPAP, from a system level perspective. It has been manufactured in a 0.35 microm standard digital 1P-5M CMOS technology. It has been designed to achieve the high-speed and moderate-accuracy -8b- requirements of most real time -early-vision applications. External data interchange and control are completely digital. The chip contains close to four million transistors, 90% of them working in analog mode. It achieves peak computing values of 0.33TeraOPS while keeping power consumption at reasonable limits -82.5GOPS/W. Preliminary experimental results are also provided in the paper.Peer Reviewe

An improved elementary processing unit for high-density CNN-based mixed-signal microprocessors for vision

This paper presents the architecture of the Elementary Processing Unit - EPU - which has been employed to design a CNN-Based 128 × 128 Focal Plane Mixed-Signal Microprocessor for vision. The EPU contains the required building blocks to implement, on chip, vision algorithms based on the execution of linear 3 × 3 convolution masks,1 or information propagative CNN templates.2 Using this EPU, we have designed a prototype, called ACE16k, which contains an array of 128 × 128 EPUs and a completely digital interface, in a standard fully-digital 0.35 μm CMOS technology. The estimation results forecast 300 GOPS, 3.23 GOPS/mm2 and 100 GOP/J.Peer Reviewe

Architectural and basic circuit considerations for a flexible 128 × 128 mixed-signal SIMD vision chip

From a system level perspective, this paper presents a 128 × 128 flexible and reconfigurable Focal-Plane Analog Programmable Array Processor, which has been designed as a single chip in a 0.35 μm standard digital 1P-5M CMOS technology. The core processing array has been designed to achieve high-speed of operation and large-enough accuracy (∼7 bits) with low power consumption. The chip includes on-chip program memory to allow for the execution of complex, sequential and/or bifurcation flow image processing algorithms. It also includes the structures and circuits needed to guarantee its embedding into conventional digital hosting systems: external data interchange and control are completely digital. The chip contains close to four million transistors, 90% of them working in analog mode. The chip features up to 330 GOPs (Giga Operations per second), and uses the power supply (180 GOP/Joule) and the silicon area (3.8 GOPS/mm2) efficiently, and is able to maintain VGA processing throughputs of 100 Frames/s with about 10-20 basic image processing tasks on each frame.This work has been supported partially funded by ONR Project N00014-00-10429 (POAC). CE Project IST-1999-19007 (DICTAM) and the Spanish MCyT Project TICI999-0826.Peer Reviewe

Mismatch-induced trade-offs and scalability of analog preprocessing visual microprocessor chips

This paper explores trade-offs associated with the scaling of the interaction circuits (synaptic transcon-ductance multipliers) in visual microprocessor chips. These trade-offs are related to the necessity of maintaining analog accuracy of these circuits while taking advantage of the possibility of reducing power consumption, increasing operational speed, and reducing the area occupation, as technologies scale down into the deep submicron range. The paper does not aim to forecast the evolution of the design of general analog and mixed-signal integrated circuits in submicron technologies. It focuses on a very specific aspect of a particular type of systems. Hence, although the conclusions of the paper might appear somewhat pessimistic, deep submicron technologies define scenarios, not covered in this paper, where analog and mixed-signal circuits can take significant advantages from technology scaling. Even for the systems targeted in this paper, improvements in terms of power consumption and overall operational speed can be achieved through the use of newer architectures and circuit techniques.This work has been partially funded by ONR Project N00014-00-10429 (POAC, CE Project IST-1999-19007 (DICTAM) and Spanish MCyT Project TICI1999-0826.Peer Reviewe